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204B协议SYNC~信号定义
204B协议里，定义了SYNC信号。Receiver设备向Transmitter驱动单独的 SYNC~ 信号。Receiver在初始同步过程中使用 SYNC~ 信号来指示错误，并在无法纠正错误条件时请求重新初始化链路。区分错误和重新初始化请求对 SYNC~ 时序提出了与帧时钟相关的要求。SYNC~ 是JESD204A与多个TX设备链路上（JESD204B 的子类 0）中的时间关键信号。为了使所有TX设备之间的 /A/ 字符对齐，所有TX设备应在同一帧周期内看到 SYNC~ 的上升沿。此外，在子类2中，SYNC~信号还兼作Receiver和Transmitter之间的定时信息载体，因此需要仔细考虑接收器内部SYNC~的生成时序及其传播到发射器的时序。
我根据对SYNC的理解，与大家分享一下学习过程，有不正确的地方，欢迎指正。
- 1SYNC~信号的发起者为RX设备
“The SYNC interface is used as a time-critical return path from receiver(s) to transmitter(s). ”SYNC信号都是从RX设备发送到TX设备，如下图B.１和B.２所示。
1.2 SYNC~需要同步到Frame clock
“It shall be synchronous with the internal frame clock of the RX device.”
如下图所示，假设F=4，即Frame包括4个byte，假设根据线速率后，可以画出frame clock的波形。
Frame Clock and Multiframe clock shall comply with the following requirements:
? The frame period in all transmitter and receiver devices must be identical
? The multiframe period in all transmitter and receiver devices must be identical
? All frame clocks and multiframe clocks in the JESD204 system must be derived from a common clock source.
? In each device, the frame clock and LMFC must be phase-aligned to each other.
? The phase of the frame clock and LMFC shall be dictated by the device clock edge upon which the SYSREF signal is detected as being active (for Subclass 1 devices).
? frame 时钟和 LMFC 的相位应由检测到 SYSREF 信号处于活动状态的设备时钟边沿决定（对于子类 1 设备）。
? The phase of the frame clock shall be dictated by the “adjustment clock” (6.4.1.2) edge following the detection of the SYNC~ de-assertion. (for Subclass 2 devices)
? Devices may optionally allow the LMFC (and Frame Clock) phase alignment to be adjusted in fine-grained increments. This is to provide flexibility in perfectly aligning LMFCs within all devices in a system.
1.3 SYNC~的同步性
“It is strongly recommended that synchronicity be maintained with the TX frame clock as well if specific clauses requiring informational passage over the SYNC interface (required for Subclass 0 and Subclass 2 operation) are to be supported.”
强烈建议使用TX Frame Clock保持信号的同步性。当需要用SYNC~信号传递特消息时（子类 0 和子类 2 操作需要），也使用TX Frame Clock保持信号的同步性。
1.4 SYNC~电气属性
“It is also strongly recommended to use a similar interface for the SYNC interface and the device clock, in order to maintain an accurate timing relationship (with the exception that SYNC~ should never be AC-coupled).”
SYNC~信号的接口特性应该与device clock相同，且从不被交流AC耦合；
1.5 SYNC~的符号表示
“The SYNC interface contains exactly one signal, which is denoted by SYNC~. The tilde indicates that the signal is active low. In case of a differential interface, the true part of the signal is active low.”
SYNC信号是低电平有效的信号，所以带有波浪线~作为后缀；使用差分信号形式的SYNC时，其真实有效电平也应该是低电平。
???????1.6 SYNC~时序图
Figure 11 shows the critical timing specifications relating to the SYNC~ signal that are necessary for both Subclass 0, due to backward compatibility to JESD204A, and Subclass 2 deterministic latency devices. The values for these parameters are not specified here but the Transmitter and Receiver device specifications shall specify these values.
tDS_R (min/max): Device-Clock-to-SYNC~ Delay at Receiver device pins. Subclass 0 and Subclass 2 Receiver devices must specify this parameter.
tSU_T (min) and tH_T (min): Setup and Hold times of SYNC~ with respect to Device Clock at the Transmitter device pins. Subclass 0 and Subclass 2 Transmitter devices must specify these parameters.
???????1.7 SYNC~的发起和采样时钟
实现204B协议的系统，其各个device只要求一个device clock作为时钟源，且每个device的device clock可能不同频率，但一定是同源的。每个device内部都有一个起源于device clock的frame clock，当frame clock的频率比device clock高时，使用frame clock发起或者采样SYNC，否者使用device clock。
The frame clock is aligned to the device clock for at least one edge per multi-frame.
This edge of the device clock is associated to an edge of the frame clock, and measurements can be taken relative to it.
All other timing is relative to this basis and will differ by some number of frame periods (Tf).
Figure 12 shows edge associations for two RX SYNC~ launch cases. In the first case, the frame clock is slower than the device clock. In the second, the device clock is slower than the frame clock.
2、SYNC~ signal combining
包含多个lanes的同一链路上的所有接收器（例如FPGA作为数据采集时），其发出的同步请求被组合成一个信号，并同时呈现给发射器设备（例如ADC）。
在多点链路上（例如一个FPGA，多个ADC芯片时（每个ADC芯片可以包含N个ADC模数转换模块）），允许但不强制合并各个链路的同步请求。多点链路中的 SYNC~ 信号组合选项概述如下：
? 在接收器逻辑器件内部（例如FPGA作为数据采集时），来自逻辑器件中每个链路的 SYNC~ 信号应组合并分发到所有 ADC，或作为单独的每链路 SYNC~ 信号分配给每个 ADC。
? 在发射逻辑器件内部（例如FPGA作为数据输出时），来自所有DAC器件的SYNC~信号可以先解码，然后组合后送给发射逻辑器件中，也可以被视为单独的每链路SYNC~信号。
图33提供了SYNC~信号组合的示例。图 34 提供了非组合 SYNC~ 信令的示例。
当使用SYNC~信号组合时，只要单个接收器请求代码组同步，所有连接到多点链路的发射器都会发送/K28.5/符号。
不使用 SYNC~ 信号组合时，只会影响请求代码组同步的特定链路。
For multipoint links, if deterministic latency is not implemented (namely, JESD204A and subclass 0 applications), SYNC~ signal combining must be used to ensure that transmitter ILA generation is properly aligned across all links.
对于多点链路，如果未实现确定性延迟（即JESD204A和子类0应用），则必须使用SYNC~信号组合来确保发送器ILA生成在所有链路上正确对齐。
